Datasheet

ADSP-21160N
–30– REV. 0
Three-State Timing—Bus Master, Bus Slave
See Table 17 and Figure 20. These specifications show how the
memory interface is disabled (stops driving) or enabled (resumes
driving) relative to CLKIN and the
SBTS pin. This timing is
applicable to bus master transition cycles (BTC) and host tran-
sition cycles (HTC) as well as the
SBTS pin.
Table 17. Three-State Timing—Bus Master, Bus Slave
Parameter Min Max Unit
Timing Requirements
t
STSCK
SBTS Setup Before CLKIN 6 ns
t
HTSCK
SBTS Hold After CLKIN 2 ns
Switching Characteristics
t
MIENA
Address/Select Enable After CLKIN 1.5 9 ns
t
MIENS
Strobes Enable After CLKIN
1
1.5 9 ns
t
MIENHG
HBG Enable After CLKIN 1.5 9 ns
t
MITRA
Address/Select Disable After CLKIN 0.5 9 ns
t
MITRS
Strobes Disable After CLKIN
1, 2
0.25t
CCLK
– 4 0.25t
CCLK
+1.5 ns
t
MITRHG
HBG Disable After CLKIN 0.5 8 ns
t
DATEN
Data Enable After CLKIN
3
0.25t
CCLK
+1 0.25t
CCLK
+7 ns
t
DATTR
Data Disable After CLKIN
3
0.5 5 ns
t
ACKEN
ACK Enable After CLKIN
3
1.5 9 ns
t
ACKTR
ACK Disable After CLKIN
3
1.5 5 ns
t
CDCEN
CLKOUT Enable After CLKIN 0.5 9 ns
t
CDCTR
CLKOUT Disable After CLKIN t
CCLK
–3 t
CCLK
+1 ns
t
ATRHBG
Address, MSx Disable Before HBG Low 1.5t
CK
–6 1.5t
CK
+ 5 ns
t
STRHBG
RDx, WRx, DMAGx Disable Before HBG Low t
CK
+ 0.25t
CCLK
–6 t
CK
+ 0.25t
CCLK
+ 5 ns
t
PTRHBG
Page Disable Before HBG Low t
CK
–6 t
CK
+ 5 ns
t
BTRHBG
BMS Disable Before HBG Low 0.5t
CK
–6.5 0.5t
CK
+ 1.5 ns
t
MENHBG
Memory Interface Enable After HBG High
4
t
CK
–5 t
CK
+6 ns
1
Strobes = RDx, WRx, DMAGx.
2
If access aborted by SBTS, then strobes disable before CLKIN [0.25t
CCLK
+ 1.5 (min.), 0.25t
CCLK
+ 5 (max.)]
3
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
4
Memory Interface = Address, RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode).