Datasheet

Rev. C | Page 14 of 60 | January 2013
ADSP-21161N
SPIDS I Serial Peripheral Interface Slave Device Select. An active low signal used to enable slave devices. This input
signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster
mode SPIDS signal can be asserted to a master device to signal that an error has occurred, as some other
device is also trying to be the master device. If asserted low when the device is in master mode, it is considered
a multimaster error. For a single-master, multiple-slave configuration where FLAG3–0 are used, this pin must
be tied or pulled high to V
DDEXT
on the master device. For ADSP-21161N to ADSP-21161N SPI interaction, any
of the master ADSP-21161N’s FLAG3–0 pins can be used to drive the SPIDS signal on the ADSP-21161N SPI
slave device.
MOSI I/O (o/d) SPI Master Out Slave. If the ADSP-21161N is configured as a master, the MOSI pin becomes a data transmit
(output) pin, transmitting output data. If the ADSP-21161N is configured as a slave, the MOSI pin becomes a
data receive (input) pin, receiving input data. In an ADSP-21161N SPI interconnection, the data is shifted out
from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has an internal
pull-up resistor.
MISO I/O (o/d) SPI Master In Slave Out. If the ADSP-21161N is configured as a master, the MISO pin becomes a data receive
(input) pin, receiving input data. If the ADSP-21161N is configured as a slave, the MISO pin becomes a data
transmit (output) pin, transmitting output data. In an ADSP-21161N SPI interconnection, the data is shifted
out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has an
internal pull-up resistor. MISO can be configured as o/d by setting the OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time.
LxDAT7–0
[DATA15–0]
I/O
[I/O/T]
Link Port Data (Link Ports 0–1).
For silicon revisions 1.2 and higher, each LxDAT pin has a keeper latch that is enabled when used as a data
pin; or a 20 k internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.
For silicon revisions 0.3, 1.0, and 1.1 each LxDAT pin has a 50 k internal pull-down resistor that is enabled
or disabled by the LxPDRDE bit of the LCTL register.
Note: L1DAT7–0 are multiplexed with the DATA15–8 pins L0DAT7–0 are multiplexed with the DATA7–0 pins. If link
ports are disabled and are not used, these pins can be used as additional data lines for executing instructions at
up to the full clock rate from external memory. See DATA47–16 for more information.
LxCLK I/O Link Port Clock (Link Ports 0–1). Each LxCLK pin has an internal pull-down 50 k resistor that is enabled or
disabled by the LxPDRDE bit of the LCTL register.
LxACK I/O Link Port Acknowledge (Link Ports 0–1). Each LxACK pin has an internal pull-down 50 k resistor that is
enabled or disabled by the LxPDRDE bit of the LCTL register.
EBOOT I EPROM Boot Select. For a description of how this pin operates, see the table in the BMS
pin description. This
signal is a system configuration selection that should be hardwired.
LBOOT I Link Boot. For a description of how this pin operates, see the table in the BMS
pin description. This signal is
a system configuration selection that should be hardwired.
BMS
I/O/T Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins (see Table 4).
This input is a system configuration selection that should be hardwired. For Host and PROM boot, DMA
channel 10 (EPB0) is used. For Link boot and SPI boot, DMA channel 8 is used.
Three-state only in EPROM boot mode (when BMS
is an output).
CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21161N clock input. It configures the ADSP-
21161N to use either its internal clock generator or an external clock source. Connecting the necessary
components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN
while leaving XTAL unconnected configures the ADSP-21161N to use the external clock source such as an
external clock oscillator.The ADSP-21161N external port cycles at the frequency of CLKIN. The instruction
cycle rate is a multiple of the CLKIN frequency; it is programmable at power-up via the CLK_CFG1–0 pins.
CLKIN may not be halted, changed, or operated below the specified frequency.
XTAL O Crystal Oscillator Terminal 2. Used in conjunction with CLKIN to enable the ADSP-21161N’s internal clock
oscillator or to disable it to use an external clock source. See CLKIN.
CLK_CFG1-0 I Core/CLKIN Ratio Control. ADSP-21161N core clock (instruction cycle) rate is equal to n  PLLICLK where
n is user selectable to 2, 3, or 4, using the CLK_CFG1–0 inputs. These pins can also be used in combination
with the CLKDBL
pin to generate additional core clock rates of 6  CLKIN and 8  CLKIN (see the Clock Rate
Ratios table in the CLKDBL
description).
Table 2. Pin Function Descriptions (Continued)
Pin Type Function