Datasheet

ADSP-21161N
Rev. C | Page 27 of 60 | January 2013
Memory Read — Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN except for ACK pin requirements listed in footnote 4 of
Table 16. These specifications apply when the ADSP-21161N is
the bus master accessing external memory space in asynchro-
nous access mode.
Table 16. Memory Read — Bus Master
100 MHz 110 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
DAD
Address, Selects Delay to
Data Valid
1, 2, 3
t
CKOP
–0.25t
CCLK
–8.5+W t
CKOP
–0.25t
CCLK
–6.75+W ns
t
DRLD
RD Low to Data Valid
1,3
0.75t
CKOP
–11+W 0.75t
CKOP
–11+W ns
t
HDA
Data Hold from Address,
Selects
4
00ns
t
SDS
Data Setup to RD High88ns
t
HDRH
Data Hold from RD High
4
11ns
t
DAAK
ACK Delay from Address,
Selects
2, 5
t
CKOP
–0.5t
CCLK
–12+W t
CKOP
–0.5t
CCLK
–12+W ns
t
DSAK
ACK Delay from RD Low
5
t
CKOP
–0.75t
CCLK
–11+W t
CKOP
–0.75t
CCLK
–11+W ns
t
SAKC
ACK Setup to CLKIN
5
0.5t
CCLK
+3 0.5t
CCLK
+3 ns
t
HAKC
ACK Hold After CLKIN 1 1 ns
Switching Characteristics
t
DRHA
Address Selects Hold
After RD High
0.25t
CCLK
–1+H 0.25t
CCLK
–1+H ns
t
DARL
Address Selects to RD
Low
2
0.25t
CCLK
–3 0.25t
CCLK
–3 ns
t
RW
RD Pulsewidth t
CKOP
–0.5t
CCLK
–1+W t
CKOP
–0.5t
CCLK
–1+W ns
t
RWR
RD High to WR, RD,
DMAGx Low
0.5t
CCLK
–1+HI 0.5t
CCLK
–1+HI ns
W = (number of wait states specified in WAIT register) × t
CKOP
.
HI = t
CKOP
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t
CKOP
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1
Data Delay/Setup: User must meet t
DAD
, t
DRLD
, or t
SDS.
2
The falling edge of MSx, BMS is referenced.
3
The maximum limits of timing requirement values for t
DAD
and t
DRLD
parameters are applicable for the case where ACK is always high.
4
Data Hold: User must meet t
HDA
or t
HDRH
in asynchronous access mode. See Example System Hold Time Calculation on Page 54 for the calculation of hold times given capacitive
and dc loads.
5
For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,
ACK must be driven low (deasserted) by t
DAAK
, t
DSAK
, or t
SAKC
. For the second and subsequent cycles of an asynchronous external memory access, the t
SAKC
and t
HAKC
must be
met for both assertion and deassertion of ACK signal.