Datasheet

ADSP-21161N
Rev. C | Page 29 of 60 | January 2013
Memory Write — Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN except for ACK pin requirements listed in footnote 1 of
Table 17. These specifications apply when the ADSP-21161N is
the bus master accessing external memory space in asynchro-
nous access mode.
Table 17. Memory Write — Bus Master
Parameter Min Max Unit
Timing Requirements
t
DAAK
ACK Delay from Address, Selects
1, 2
t
CKOP
–0.5t
CCLK
–12+W ns
t
DSAK
ACK Delay from WR Low
1
t
CKOP
–0.75t
CCLK
–11+W ns
t
SAKC
ACK Setup to CLKIN
1
0.5t
CCLK
+3 ns
t
HAKC
ACK Hold After CLKIN
1
1ns
Switching Characteristics
t
DAWH
Address, Selects to WR Deasserted
2
t
CKOP
–0.25t
CCLK
–3+W ns
t
DAWL
Address, Selects to WR Low
2
0.25t
CCLK
–3 ns
t
WW
WR Pulsewidth t
CKOP
–0.5t
CCLK
–1+W ns
t
DDWH
Data Setup Before WR High t
CKOP
–0.25t
CCLK
–13.5+W ns
t
DWHA
Address Hold After WR Deasserted 0.25t
CCLK
–1+H ns
t
DWHD
Data Hold After WR Deasserted 0.25t
CCLK
–1+H ns
t
DATRWH
Data Disable After WR Deasserted
3
0.25t
CCLK
– 2+H 0.25t
CCLK
+2.5+H ns
t
WWR
WR High to WR, RD, DMAGx Low 0.5t
CCLK
–1.25+HI ns
t
DDWR
Data Disable Before WR or RD Low 0.25t
CCLK
–3+I ns
t
WDE
WR Low to Data Enabled –0.25t
CCLK
–1 ns
W = (number of wait states specified in WAIT register) × t
CKOP
.
H = t
CKOP
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = t
CKOP
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = t
CKOP
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1
For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,
ACK must be driven low (deasserted) by t
DAAK
, t
DSAK
, or t
SAKC
. For the second and subsequent cycles of an asynchronous external memory access, the t
SAKC
and t
HAKC
must be
met for both assertion and deassertion of ACK signal.
2
The falling edge of MSx, BMS is referenced.
3
See Example System Hold Time Calculation on Page 54 for calculation of hold times given capacitive and dc loads.