Datasheet

Rev. C | Page 32 of 60 | January 2013
ADSP-21161N
Synchronous Read/Write — Bus Slave
Use these specifications for ADSP-21161N bus master accesses
of a slave’s IOP registers in multiprocessor memory space. The
bus master must meet these (bus slave) timing requirements.
Table 19. Synchronous Read/Write — Bus Slave
Parameter Min Max Unit
Timing Requirements
t
SADDI
Address, BRST Setup Before CLKIN 5 ns
t
HADDI
Address, BRST Hold After CLKIN 1 ns
t
SRWI
RD/WR Setup Before CLKIN 5 ns
t
HRWI
RD/WR Hold After CLKIN 1 ns
t
SSDATI
Data Setup Before CLKIN 5.5 ns
t
HSDATI
Data Hold After CLKIN 1 ns
Switching Characteristics
t
DDATO
Data Delay After CLKIN 12.5 ns
t
HDATO
Data Hold After CLKIN 1.5 ns
t
DACKC
ACK Delay After CLKIN 10 ns
t
HACKO
ACK Hold After CLKIN 1.5 ns
Figure 20. Synchronous Read/Write — Bus Slave
CLKIN
ADDRESS
ACK
DATA
(OUT)
WRITE ACCESS
DATA
(IN)
READ ACCESS
t
SADDI
t
HADDI
t
DACKC
t
HACKO
t
HRWI
t
SRWI
t
DDATO
t
HDATO
t
SRWI
t
HRWI
t
HSDATI
t
SSDATI
RD
WR