Datasheet

ADSP-21161N
Rev. C | Page 35 of 60 | January 2013
Multiprocessor Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-21161Ns (BRx
).
Table 21. Multiprocessor Bus Request
Parameter Min Max Unit
Timing Requirements
t
SBRI
BRx Setup Before CLKIN High 9 ns
t
HBRI
BRx Hold After CLKIN High 0.5 ns
t
SPAI
PA Setup Before CLKIN High 9 ns
t
HPAI
PA Hold After CLKIN High 1 ns
t
SRPBAI
RPBA Setup Before CLKIN High 6 ns
t
HRPBAI
RPBA Hold After CLKIN High 2 ns
Switching Characteristics
t
DBRO
BRx Delay After CLKIN High 8 ns
t
HBRO
BRx Hold After CLKIN High 1.0 ns
t
DPASO
PA Delay After CLKIN High, Slave 8 ns
t
TRPAS
PA Disable After CLKIN High, Slave 1.5 ns
t
DPAMO
PA Delay After CLKIN High, Master 0.25t
CCLK
+9 ns
t
PAT R
PA Disable Before CLKIN High, Master 0.25t
CCLK
–5 ns
Figure 22. Multiprocessor Bus Request
t
HBRI
RP BA
O/D = OP EN DRAIN
t
HR P B AI
t
S RPBAI
t
SBRI
CLKIN
PA (OUT)
(SLA V E)
t
DBRO
t
HBRO
t
DP A SO
t
TRPAS
PA (OUT)
(MASTER)
t
DPAMO
t
PATR
PA (IN)
(O/D)
t
HPAI
t
S PAI
BRx (OUT)
BR x (IN)