Datasheet

ADSP-21161N
Rev. C | Page 39 of 60 | January 2013
Figure 24. Three-State Timing — Bus Master, Bus Slave
CLKIN
ACK
MEMORY
INTERFACE
CLKOUT
t
CDCTR
DATA
MEMORY
INTERFACE
t
MITRA,
t
MITRS,
t
MITRHG
t
HTSCK
t
CDCEN
t
MIENA,
t
MIENS,
t
MIENHG
CLKIN
t
ATRHBG,
t
STRHBG,
t
BTRHBG
t
STSCK
t
DATEN
t
ACKEN
t
DATTR
t
ACKTR
t
MENHBG
SBTS
HBG
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, DMAGx, BMS (IN EPROM MODE)