Datasheet

Rev. C | Page 48 of 60 | January 2013
ADSP-21161N
Figure 29. Serial Ports
DRIVE EDGE
SCLK (INT)
DRIVE EDGE
SCLK
DRIVE EDGE DRIVE EDGE
SCLK
SCLK (EXT)
t
DDTTE
t
DDTEN
t
DDTTI
t
DDTIN
D
X
A/D
X
B
D
X
A/D
X
B
SCLK
FS
DRIVE EDGE SAMPLE EDGE
DATA RECEIVE— INTERNAL CLOCK DATA RECEIVE— EXTERNAL CLOCK
SCLK
FS
DRIVE EDGE SAMPLE EDGE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
SDRI
t
HDRI
t
SFSI
t
HFSI
t
DFSI
t
HOFSI
t
SCLKIW
t
SDRE
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
D
X
A/D
X
B
D
X
A/D
X
B
t
DDTI
SCLK
FS
DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT — INTERNAL CLOCK
t
SFSI
t
HFSI
t
DFSI
t
HOFSI
t
SCLKIW
D
X
A/D
X
B
t
HDTI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE S AMPLING EDGE.
t
DDTE
SCLK
FS
DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT — EXTERNAL CLOCK
t
SFSE
t
HFSE
t
DFSE
t
HOFSE
t
SCLKW
D
X
A/D
X
B
t
HDTE