Datasheet

ADSP-21161N
Rev. C | Page 51 of 60 | January 2013
Table 37. SPI Interface Protocol — Slave Switching and Timing
Parameter Min Max Unit
Timing Requirements
t
SPICLKS
Serial Clock Cycle 8t
CCLK
ns
t
SPICHS
Serial Clock High Period 4t
CCLK
–4 ns
t
SPICLS
Serial Clock Low Period 4t
CCLK
–4 ns
t
SDSCO
SPIDS Assertion to First SPICLK Edge
CPHASE = 0 3.5t
CCLK
+8 ns
CPHASE = 1 1.5t
CCLK
+8 ns
t
HDS
Last SPICLK Edge to SPIDS Not Asserted
CPHASE = 0 0 ns
t
SSPIDS
Data Input Valid to SPICLK Edge (Data Input Set-up Time) 0 ns
t
HSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid t
CCLK
+1 ns
t
SDPPW
SPIDS Deassertion Pulsewidth (CPHASE = 0) t
CCLK
ns
Switching Characteristics
t
DSOE
SPIDS Assertion to Data Out Active 2 0.5t
CCLK
+5.5 ns
t
DSDHI
SPIDS Deassertion to Data High Impedance 1.5 0.5t
CCLK
+5.5 ns
t
DDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time) 0.75t
CCLK
+3 ns
t
HDSPIDS
1
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 0.25t
CCLK
+3 ns
t
HDLSBS
1
SPICLK Edge to Last Bit Out Not Valid
(Data Out Hold Time) for LSB 0.5t
SPICLK
+4.5t
CCLK
ns
t
DSOV
2
SPIDS Assertion to Data Out Valid (CPHASE = 0) 1.5t
CCLK
+7 ns
1
When CPHASE = 0 and baud rate is greater than 1, t
HDLSBS
affects the length of the last bit transmitted.
2
Applies to the first deassertion of SPIDS only.