Datasheet

Rev. C | Page 52 of 60 | January 2013
ADSP-21161N
Figure 32. SPI Interface Protocol — Slave Switching and Timing
t
HS PIDS
t
DDSPIDS
t
DS DHI
LSBMSB
MSBVALID
t
DS OE
t
DDS PIDS
t
HDS PIDS
MISO
(OUTPUT)
MOSI
(INPUT)
t
SSPIDS
SPIDS
(INPUT)
SPICLK
(CP = 0)
(INPUT)
SPICLK
(CP = 1)
(INPUT)
t
S D S CO
t
S PICHS
t
S PICLS
t
S PICLS
t
S PICLKS
t
HDS
t
S PICHS
t
SSPIDS
t
H S PIDS
t
DS DHI
LSBVALID
MSB
MSBVALID
t
D S OE
t
DDS PIDS
MISO
(OUTPUT)
MOSI
(INPUT)
t
SSPIDS
LSBVALID
LSB
CPHASE=1
CPHASE=0
t
S DPPW
t
D S OV
t
HDS PIDS
t
HDLS B S