Datasheet

Rev. G | Page 24 of 48 | December 2012
ADSP-21261/ADSP-21262/ADSP-21266
Memory Read—Parallel Port
The specifications in Table 25, Table 26, Figure 16, and
Figure 17 are for asynchronous interfacing to memories (and
memory-mapped peripherals) when the ADSP-2126x is access-
ing external memory space.
Table 25. 8-Bit Memory Read Cycle
Parameter Min Max Unit
Timing Requirements
t
DRS
Address/Data 7–0 Setup Before RD High 3.3 ns
t
DRH
Address/Data 7–0 Hold After RD High 0 ns
t
DAD
Address 15–8 to Data Valid D + 0.5 × t
CCLK
– 3.5 ns
Switching Characteristics
t
ALEW
ALE Pulse Width 2 × t
CCLK
– 2 ns
t
ALERW
ALE Deasserted to Read/Write Asserted 1 × t
CCLK
– 0.5 ns
t
ADAS
1
Address/Data 15–0 Setup Before ALE Deasserted 2.5 × t
CCLK
– 2.0 ns
t
ADAH
1 Address/Data 15–0 Hold After ALE Deasserted 0.5 × t
CCLK
– 0.8 ns
t
ALEHZ
1
ALE Deasserted to Address/Data7–0 in High-Z 0.5 × t
CCLK
– 0.8 0.5 × t
CCLK
+ 2.0 ns
t
RW
RD Pulse Width D – 2 ns
t
ADRH
Address/Data 15–8 Hold After RD High 0.5 × t
CCLK
– 1 + H ns
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
CCLK
H = t
CCLK
(if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Figure 16. 8-Bit Memory Read Cycle
AD15-8
ALE
RD
WR
AD7-0
VALID ADDRESS
VALID ADDRESS
t
ALEW
t
ALERW
t
RW
t
ALEHZ
t
ADAH
t
ADAS
t
ADRH
t
DRH
t
DRS
VALID ADDRESS
t
DAD
VALID DATA