Datasheet

ADSP-21261/ADSP-21262/ADSP-21266
Rev. G | Page 11 of 48 | December 2012
SPICLK I/O Three-state with
pull-up enabled,
driven high in SPI-
master boot mode
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the
rate at which data is transferred. The master can transmit data at a variety of baud rates.
SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during
data transfers, only for the length of the transferred word. Slave devices ignore the serial
clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and shift
in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock
edge and sampled on the opposite edge of the clock. Clock polarity and clock phase
relative to data are programmable into the SPICTL control register and define the transfer
format. SPICLK has a 22.5 k internal pull-up resistor. If SPI master boot mode is selected,
MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset
in SPI master boot mode.
SPIDS
IInput onlySerial Peripheral Interface Slave Device Select. An active low signal used to select the
DSP as an SPI slave device. This input signal behaves like a chip select, and is provided by
the master device for the slave devices. In multimaster mode, the DSP’s SPIDS
signal can
be driven by a slave device to signal to the DSP (as SPI master) that an error has occurred,
as some other device is also trying to be the master device. If asserted low when the
device is in master mode, it is considered a multimaster error. For a single master,
multiple-slave configuration where flag pins are used, this pin must be tied or pulled high
to V
DDEXT
on the master device. For ADSP-2126x to ADSP-2126x SPI interaction, any of the
master ADSP-2126x’s flag pins can be used to drive the SPIDS signal on the ADSP-2126x
SPI slave device.
MOSI I/O (O/D) Three-state with
pull-up enabled,
driven low in SPI-
master boot mode
SPI Master Out Slave In. If the ADSP-2126x is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-2126x is
configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input
data. In an ADSP-2126x SPI interconnection, the data is shifted out from the MOSI output
pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 k
internal pull-up resistor. If SPI master boot mode is selected, MOSI and SPICLK pins are
driven during reset. These pins are not three-stated during reset in SPI master boot mode.
MISO I/O (O/D) Three-state with
pull-up enabled
SPI Master In Slave Out. If the ADSP-2126x is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-2126x is configured
as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data.
In an ADSP-2126x SPI interconnection, the data is shifted out from the MISO output pin
of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 k internal
pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL
register.
Note: Only one slave is allowed to transmit data at any given time. To enable broadcast
transmission to multiple SPI slaves, the DSP’s MISO pin can be disabled by setting (= 1)
Bit 5 (DMISO) of the SPICTL register.
BOOT_CFG1–0 I Input only Boot Configuration Select. Selects the boot mode for the DSP. The BOOT_CFG pins must
be valid before reset is asserted. See Table 8 on Page 13 for a description of the boot
modes.
CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2126x clock input. It
configures the ADSP-2126x to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected
configures the ADSP-2126x to use the external clock source such as an external clock
oscillator. The core is clocked either by the PLL output or this clock input depending on
the CLK_CFG1–0 pin settings. CLKIN should not be halted, changed, or operated below
the specified frequency.
XTAL O Output only
2
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
Table 6. Pin Descriptions (Continued)
Pin Type
State During and
After Reset Function