Datasheet

ADSP-21261/ADSP-21262/ADSP-21266
Rev. G | Page 15 of 48 | December 2012
PACKAGE INFORMATION
The information presented in Figure 3 provides details about
the package branding for the ADSP-21266 processors. For a
complete listing of product availability, see Ordering Guide on
Page 45.
ESD CAUTION
MAXIMUM POWER DISSIPATION
See Estimating Power for the ADSP-21262 SHARC Processors
(EE-216) for detailed thermal and power information regarding
maximum power dissipation. For information on package ther-
mal specifications, see Thermal Characteristics on Page 38.
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 12 may cause perma-
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times.
Timing requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Switching characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core,
serial ports, and parallel port (as required for read/write strobes
in asynchronous access mode). During reset, program the ratio
between the DSP’s internal clock frequency and external
(CLKIN) clock frequency with the CLK_CFG1–0 pins. To
determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the DSP uses an internal phase-locked loop (PLL). This
PLL-based clocking minimizes the skew between the system
clock (CLKIN) signal and the DSP’s internal clock (the clock
source for the parallel port logic and I/O pads).
Figure 3. Typical Package Brand
Table 11. Package Brand Information
Brand Key Field Description
t Temperature Range
pp Package Type
Z RoHS Compliant Option (optional)
cc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
# RoHS Compliant Designation
yyww Date Code
vvvvvv.x n.n
tppZ-cc
S
ADSP-2126x
a
#yyww country_of_origin
ESD
(electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid
performance degradation or loss of functionality.
Table 12. Absolute Maximum Ratings
Parameter Rating
Internal (Core) Supply Voltage (V
DDINT
) –0.3 V to +1.4 V
Analog (PLL) Supply Voltage (A
VDD
) –0.3 V to +1.4 V
External (I/O) Supply Voltage (V
DDEXT
)–0.3 V to +3.8 V
Input Voltage –0.5 V to V
DDEXT
+0.5 V
Output Voltage Swing –0.5 V to V
DDEXT
+0.5 V
Load Capacitance 200 pF
Storage Temperature Range –65C to +150C
Junction Temperature Under Bias 125C