Datasheet

Rev. G | Page 16 of 48 | December 2012
ADSP-21261/ADSP-21262/ADSP-21266
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f
VCO
specified in Table 16.
• The product of CLKIN and PLLM must never exceed 1/2 of
f
VCO
(max) in Table 16 if the input divider is not enabled
(INDIV = 0).
• The product of CLKIN and PLLM must never exceed f
VCO
(max) in Table 16 if the input divider is enabled
(INDIV = 1).
The VCO frequency is calculated as follows:
f
VCO
= 2  PLLM  f
INPUT
f
CCLK
= (2  PLLM  f
INPUT
)  (2  PLLD)
where:
f
VCO
= VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 2, 4, 8, 16 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
f
INPUT
= is the input frequency to the PLL.
f
INPUT
= CLKIN when the input divider is disabled or
f
INPUT
= CLKIN  2 when the input divider is enabled
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control shown in Table 13
and Table 14.
Figure 4 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2126x SHARC Processor
Peripherals Reference and Managing the Core PLL on Third-
Generation SHARC Processors (EE-290).
Table 13. CLKOUT and CCLK Clock Generation Operation
Timing
Requirements Description Calculation
CLKIN Input Clock 1/t
CK
CCLK Core Clock Variable, see equation
Table 14. Clock Periods
Timing
Requirements Description
1
t
CK
CLKIN Clock Period
t
CCLK
(Processor) Core Clock Period
t
MCLK
Internal memory clock = 1/2 t
CCLK
t
SCLK
Serial Port Clock Period = (t
CCLK
) × SR
t
SPICLK
SPI Clock Period = (t
CCLK
) × SPIR
1
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT
CLKDIV)
SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register)
SCLK = serial port clock
SPICLK = SPI clock
Figure 4. Core Clock and System Clock Relationship to CLKIN
LOOP
FILTER
CLKIN
CCLK
PLL
XTAL
CLKIN
DIVIDER
RESETOUT
DELAY OF
4096 CLKIN
CYCLES
RESET
PLL
MULTIPLIER
BUF
VCO
BUF
PLLI
CLK
PMCTL
CLK_CFGx/
PMCTL
PLL
DIVIDER
CLK_CFGx/PMCTL
MUX
PIN MUX
DIVIDE
BY 2
RESETOUT
PMCTL
CLKOUT (TEST ONLY)
MCLK
CORERST