Datasheet

ADSP-21261/ADSP-21262/ADSP-21266
Rev. G | Page 17 of 48 | December 2012
Power-Up Sequencing
The timing requirements for DSP startup are given in Table 15
and Figure 5. Note that during power-up, a leakage current of
approximately 200 A may be observed on the RESET
pin. This
leakage current results from the weak internal pull-up resistor
on this pin being enabled during power-up.
Table 15. Power-Up Sequencing (DSP Startup)
Parameter Min Max Unit
Timing Requirements
t
RSTVDD
RESET Low Before V
DDINT
/V
DDEXT
On 0 ns
t
IVDDEVDD
V
DDINT
On Before V
DDEXT
–50 +200 ms
t
CLKVDD
CLKIN Valid After V
DDINT
/V
DDEXT
Valid
1
0200ms
t
CLKRST
CLKIN Valid Before RESET Deasserted 10
2
μs
t
PLLRST
PLL Control Setup Before RESET Deasserted 20
3
μs
Switching Characteristics
t
CORERST
DSP Core Reset Deasserted After RESET Deasserted 4096  t
CK
4, 5
1
Valid V
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.2 V and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer’s data sheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on t
SRST
specification in Table 17. If setup time is not met, one additional CLKIN cycle can be added to the core reset time, resulting in 4097
cycles maximum.
Figure 5. Power-Up Sequencing
t
RSTVDD
t
CLKVDD
t
CLKRST
t
CORERST
t
PLLRST
V
DDEXT
V
DDINT
CLKIN
CLK_CFG1–0
RESET
RESETOUT
(MUXED WITH CLKOUT)
t
IVDDEVDD