Datasheet

Rev. G | Page 18 of 48 | December 2012
ADSP-21261/ADSP-21262/ADSP-21266
Clock Input
See Table 16 and Figure 6.
Clock Signals
The ADSP-2126x can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-2126x to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL. Figure 7 shows
the component connections used for a crystal operating in fun-
damental mode. Note that the 200 MHz clock rate is achieved
using a 12.5 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN).
Table 16. Clock Input
Parameter
150 MHz
1
200 MHz
2
Unit
Min Max Min Max
Timing Requirements
t
CK
CLKIN Period 20
3
160
4
15
3
160
4
ns
t
CKL
CLKIN Width Low 7.5
3
80
4
6
3
80
4
ns
t
CKH
CLKIN Width High 7.5
3
80
4
6
3
80
4
ns
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 ns
f
vco
5
VCO Frequency 200 800 200 800 MHz
t
CCLK
CCLK Period
6
6.66 10 5 10 ns
1
Applies to all 150 MHz models. See Ordering Guide on Page 45.
2
Applies to all 200 MHz models. See Ordering Guide on Page 45.
3
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
4
Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL.
5
See Figure 4 on Page 16 for VCO diagram.
6
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
Figure 6. Clock Input
CLKIN
t
CK
t
CKL
t
CKH
Figure 7. 150 MHz or 200 MHz Operation with a 12.5 MHz
Fundamental Mode Crystal
CLKIN XTAL
C1 C2
X1
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
1M ⍀