Datasheet

ADSP-21261/ADSP-21262/ADSP-21266
Rev. G | Page 19 of 48 | December 2012
Reset
See Table 17 and Figure 8.
Interrupts
The timing specification in Table 18 and Figure 9 applies to the
FLAG0, FLAG1, and FLAG2 pins when they are configured as
IRQ0
, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1
pins when configured as interrupts.
Table 17. Reset
Parameter Min Max Unit
Timing Requirements
t
WRST
RESET Pulse Width Low
1
4  t
CK
ns
t
SRST
RESET Setup Before CLKIN Low 8 ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable
VDD and CLKIN (not including start-up time of external clock oscillator).
Figure 8. Reset
CLKIN
RESET
t
SRST
t
WRST
Table 18. Interrupts
Parameter Min Max Unit
Timing Requirements
t
IPW
IRQx Pulse Width 2 t
CCLK
+2 ns
Figure 9. Interrupts
INTERRUPT
INPUTS
t
IPW