Datasheet

Rev. G | Page 20 of 48 | December 2012
ADSP-21261/ADSP-21262/ADSP-21266
Core Timer
The timing specification in Table 19 and Figure 10 applies to
FLAG3 when it is configured as the core timer (CTIMER).
Timer PWM_OUT Cycle Timing
The timing specification in Table 20 and Figure 11 applies to
Timer in PWM_OUT (pulse-width modulation) mode. Timer
signals are routed to the DAI_P20–1 pins through the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P20–1 pins.
Table 19. Core Timer
Parameter Min Max Unit
Switching Characteristics
t
WCTIM
CTIMER Pulse Width 4 × t
CCLK
– 1 ns
Figure 10. Core Timer
FLAG3
(CTIMER)
t
WCTIM
Table 20. Timer PWM_OUT Timing
Parameter Min Max Unit
Switching Characteristics
t
PWMO
Timer Pulse Width Output 2  t
CCLK
– 1 2(2
31
– 1)  t
CCLK
ns
Figure 11. Timer PWM_OUT Timing
PWM
OUTPUTS
t
PWMO