Datasheet

ADSP-21261/ADSP-21262/ADSP-21266
Rev. G | Page 21 of 48 | December 2012
Timer WDTH_CAP Timing
The timing specification in Table 21 and Figure 12 applies to
Timer in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
DAI Pin-to-Pin Direct Routing
See Table 22 and Figure 13 for direct pin connections only (for
example, DAI_PB01_I to DAI_PB02_O).
Table 21. Timer Width Capture Timing
Parameter Min Max Unit
Timing Requirements
t
PWI
Timer Pulse Width 2 × t
CCLK
2(2
31
– 1) × t
CCLK
ns
Figure 12. Timer Width Capture Timing
TIMER
CAPTURE
INPUTS
t
PWI
Table 22. DAI Pin-to-Pin Routing
Parameter Min Max Unit
Timing Requirements
t
DPIO
Delay DAI Pin Input Valid to DAI Output Valid 1.5 10 ns
Figure 13. DAI Pin-to-Pin Direct Routing
DAI_Pn
DAI_Pm
t
DPIO