Datasheet

Rev. G | Page 22 of 48 | December 2012
ADSP-21261/ADSP-21262/ADSP-21266
Precision Clock Generator (Direct Pin Routing)
The timing in Table 23 and Figure 14 is valid only when the
SRU is configured such that the precision clock generator
(PCG) takes its inputs directly from the DAI pins (via pin buf-
fers) and sends its outputs directly to the DAI pins. For the
other cases where the PCG’s inputs and outputs are not directly
routed to/from DAI pins (via pin buffers), there is no timing
data available. All timing parameters and switching characteris-
tics apply to external DAI pins (DAI_P07–DAI_P20).
Table 23. Precision Clock Generator (Direct Pin Routing)
Parameter Min Max Unit
Timing Requirements
t
PCGIW
Input Clock Pulse Width 20 ns
t
STRIG
PCG Trigger Setup Before Falling Edge of PCG Input Clock 2 ns
t
HTRIG
PCG Trigger Hold After Falling Edge of PCG Input Clock 2 ns
Switching Characteristics
t
DPCGIO
PCG Output Clock and Frame Sync Active Edge Delay After PCG Input
Clock Falling Edge 2.5 10 ns
t
DTRIG
PCG Output Clock and Frame Sync Delay After PCG Trigger 2.5 + 2.5 × t
PCGOW
10 + 2.5 × t
PCGOW
ns
t
PCGOW
Output Clock Pulse Width 40 ns
Figure 14. Precision Clock Generator (Direct Pin Routing)
DAI_Pn
PCG_TRIGx_I
DAI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
PCK_CLKx_O
DAI_Pz
PCG_FSx_O
t
DTRIG
t
DPCGIO
t
STRIG
t
HTRIG
t
PCGOW
t
DPCGIO
t
PCGIW