Datasheet

ADSP-21261/ADSP-21262/ADSP-21266
Rev. G | Page 25 of 48 | December 2012
Table 26. 16-Bit Memory Read Cycle
Parameter Min Max Unit
Timing Requirements
t
DRS
Address/Data 15–0 Setup Before RD high 3.3 ns
t
DRH
Address/Data 15–0 Hold After RD high 0 ns
Switching Characteristics ns
t
ALEW
ALE Pulse Width 2 × t
CCLK
– 2 ns
t
ALERW
ALE Deasserted to Read/Write Asserted 1 × t
CCLK
– 0.5 ns
t
ADAS
1
Address/Data 15–0 Setup Before ALE Deasserted 2.5 × t
CCLK
– 2.0 ns
t
ADAH
1 Address/Data 15–0 Hold After ALE Deaserted 0.5 × t
CCLK
– 0.8 ns
t
ALEHZ
1
ALE Deasserted to Address/Data 15–0 in High-Z 0.5 × t
CCLK
– 0.8 0.5 × t
CCLK
+ 2.0 ns
t
RW
RD Pulse Width D – 2 ns
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
CCLK
H = t
CCLK
(if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Figure 17. 16-Bit Memory Read Cycle
AD15-0
ALE
RD
WR
VALID ADDRESS
t
ALEW
t
ALERW
t
RW
t
ALEHZ
t
ADAH
t
ADAS
t
DRH
t
DRS
VALID ADDRESS