Datasheet

Rev. G | Page 26 of 48 | December 2012
ADSP-21261/ADSP-21262/ADSP-21266
Memory Write—Parallel Port
Use the specifications in Table 27, Table 28, Figure 18, and
Figure 19 for asynchronous interfacing to memories (and
memory-mapped peripherals) when the ADSP-2126x is access-
ing external memory space.
Table 27. 8-Bit Memory Write Cycle
Parameter Min Max Unit
Switching Characteristics
t
ALEW
ALE Pulse Width 2 × t
CCLK
– 2 ns
t
ALERW
ALE Deasserted to Read/Write Asserted 1 × t
CCLK
– 0.5 ns
t
ADAS
1
Address/Data 15–0 Setup Before ALE Deasserted 2.5 × t
CCLK
– 2.0 ns
t
ADAH
1
Address/Data 15–0 Hold After ALE Deasserted 0.5 × t
CCLK
– 0.8 ns
t
WW
WR Pulse Width D – 2 ns
t
ADWL
Address/Data 15–8 to WR Low 0.5 × t
CCLK
– 1.5 ns
t
ADWH
Address/Data 15–8 Hold After WR High 0.5 × t
CCLK
– 1 + H ns
t
ALEHZ
ALE Deasserted to Address/Data 15–0 in High-Z 0.5 × t
CCLK
– 0.8 0.5 × t
CCLK
+ 2.0 ns
t
DWS
Address/Data 7–0 Setup Before WR High D ns
t
DWH
Address/Data 7–0 Hold After WR High 0.5 × t
CCLK
– 1.5 + H ns
t
DAWH
Address/Data to WR High D ns
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
CCLK
H = t
CCLK
(if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Figure 18. 8-Bit Memory Write Cycle
AD15-8
ALE
WR
RD
AD7-0
VALID ADDRESS
VALID ADDRESS
t
ALEW
t
ALERW
t
WW
t
ALEHZ
t
ADAH
t
ADAS
t
ADWH
t
DWH
t
DWS
VALID ADDRESS
t
ADWL
VALID DATA
t
DAWH