Datasheet

Rev. G | Page 28 of 48 | December 2012
ADSP-21261/ADSP-21262/ADSP-21266
Serial Ports
To determine whether communication is possible between two
devices at a given clock speed, the specifications in Table 29,
Table 30, Table 31, Table 32, Figure 20, Figure 21, and Figure 22
must be confirmed: 1) frame sync delay and frame sync setup
and hold; 2) data delay and data setup and hold; and 3) SCLK
width.
Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 29. Serial Ports—External Clock
Parameter Min Max Unit
Timing Requirements
t
SFSE
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
2.5 ns
t
HFSE
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
2.5 ns
t
SDRE
Receive Data Setup Before Receive SCLK
1
2.5 ns
t
HDRE
Receive Data Hold After SCLK
1
2.5 ns
t
SCLKW
SCLK Width 7 ns
t
SCLK
SCLK Period 20 ns
Switching Characteristics
t
DFSE
FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
2
7ns
t
HOFSE
FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
2
2ns
t
DDTE
Transmit Data Delay After Transmit SCLK
2
7ns
t
HDTE
Transmit Data Hold After Transmit SCLK
2
2ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 30. Serial Ports—Internal Clock
Parameter Min Max Unit
Timing Requirements
t
SFSI
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
6ns
t
HFSI
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
1.5 ns
t
SDRI
Receive Data Setup Before SCLK
1
6ns
t
HDRI
Receive Data Hold After SCLK
1
1.5 ns
Switching Characteristics
t
DFSI
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
2
3ns
t
HOFSI
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
2
–1.0 ns
t
DFSI
FS Delay After SCLK (Internally Generated FS in Receive Mode)
2
3ns
t
HOFSI
FS Hold After SCLK (Internally Generated FS in Receive Mode)
2
–1.0 ns
t
DDTI
Transmit Data Delay After SCLK
2
3ns
t
HDTI
Transmit Data Hold After SCLK
2
–1.0 ns
t
SCLKIW
Transmit or Receive SCLK Width 0.5t
SCLK
– 2 0.5t
SCLK
+ 2 ns
1
Referenced to the sample edge.
2
Referenced to drive edge.