Datasheet

Rev. G | Page 32 of 48 | December 2012
ADSP-21261/ADSP-21262/ADSP-21266
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 33 and
Figure 23. IDP Signals (SCLK, FS, SDATA) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 33. Input Data Port (IDP)
Parameter Min Max Unit
Timing Requirements
t
SISFS
FS Setup Before SCLK Rising Edge
1
2.5 ns
t
SIHFS
FS Hold After SCLK Rising Edge
1
2.5 ns
t
SISD
SDATA Setup Before SCLK Rising Edge
1
2.5 ns
t
SIHD
SDATA Hold After SCLK Rising Edge
1
2.5 ns
t
IDPCLKW
Clock Width 7 ns
t
IDPCLK
Clock Period 20 ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the precision clock generators (PCG) or SPORTs. PCG input can be either CLKIN or
any of the DAI pins.
Figure 23. Input Data Port (IDP)
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
t
IDPCLK
t
IDPCLKW
t
SISFS
t
SIHFS
t
SIHD
t
SISD