Datasheet

Rev. G | Page 34 of 48 | December 2012
ADSP-21261/ADSP-21262/ADSP-21266
SPI Interface Protocol—Master
Table 35. SPI Interface Protocol—Master
Parameter Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time) 5 ns
t
HSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid 2 ns
Switching Characteristics
t
SPICLKM
Serial Clock Cycle 8 × t
CCLK
ns
t
SPICHM
Serial Clock High Period 4 × t
CCLK
– 2 ns
t
SPICLM
Serial Clock Low Period 4 × t
CCLK
– 2 ns
t
DDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time) 3 ns
t
HDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 10 ns
t
SDSCIM
FLAG3–0 OUT (SPI Device Select) Low to First SPICLK Edge 4 × t
CCLK
– 2 ns
t
HDSM
Last SPICLK Edge to FLAG3–0 OUT High 4 × t
CCLK
– 1 ns
t
SPITDM
Sequential Transfer Delay 4 × t
CCLK
– 1 ns
Figure 25. SPI Interface Protocol—Master
t
SPICHM
t
SDSCIM
t
SPICLM
t
SPICLKM
t
HDSM
t
SPITDM
t
DDSPIDM
t
HSPIDM
t
SSPIDM
DPI
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
CPHASE = 1
CPHASE = 0
t
HDSPIDM
t
HSPIDM
t
HSPIDM
t
SSPIDM
t
SSPIDM
t
DDSPIDM
t
HDSPIDM
SPICLK
(CP = 0,
CP = 1)
(OUTPUT)