Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 13 of 60 | July 2013
BOOT_CFG1–0 I Input only Boot Configuration Select. This pin is used to select the boot mode for the processor.
The BOOT_CFG pins must be valid before reset is asserted. For a description of the boot
mode, refer to Table 5, Boot Mode Selection.
RESETOUT O Output only Reset Out. Drives out the core reset signal to an external device.
RESET
I/A Input only Processor Reset. Resets the ADSP-2136x to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
TCK I Input only
3
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processors.
TMS I/S
(pu)
Three-state with
pull-up enabled
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
internal pull-up resistor.
TDI I/S
(pu)
Three-state with
pull-up enabled
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 kΩ internal pull-up resistor.
TDO O Three-state
4
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
(pu)
Three-state with
pull-up enabled
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-2136x. TRST
has a 22.5 kΩ
internal pull-up resistor.
EMU
O (O/D)
(pu)
Three-state with
pull-up enabled
Emulation Status. Must be connected to the processor’s JTAG emulators target board
connector only. EMU
has a 22.5 kΩ internal pull-up resistor.
V
DDINT
P Core Power Supply. Supplies the processor’s core.
V
DDEXT
P I/O Power Supply.
A
VDD
P Analog Power Supply. Supplies the processor’s internal PLL (clock generator). This pin
has the same specifications as V
DDINT
, except that added filtering circuitry is required. For
more information, see Power Supplies on Page 8.
A
VSS
G Analog Power Supply Return.
GND G Power Supply Return.
1
RD, WR, and ALE are three-stated (and not driven) only when RESET is active.
2
Output only is a three-state driver with its output path always enabled.
3
Input only is a three-state driver with both output path and pull-up disabled.
4
Three-state is a three-state driver with pull-up disabled.
Table 6. Pin Descriptions (Continued)
Pin Type
State During and
After Reset Function
The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply,
S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor.