Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 15 of 60 | July 2013
ELECTRICAL CHARACTERISTICS
Parameter Description Test Conditions Min Max Unit
V
OH
1
High Level Output Voltage @ V
DDEXT
= Min, I
OH
= –1.0 mA
2
2.4 V
V
OL
1
Low Level Output Voltage @ V
DDEXT
= Min, I
OL
= 1.0 mA
2
0.4 V
I
IH
3, 4
High Level Input Current @ V
DDEXT
= Max, V
IN
= V
DDEXT
Max 10 μA
I
IL
3
Low Level Input Current @ V
DDEXT
= Max, V
IN
= 0 V 10 μA
I
ILPU
4
Low Level Input Current Pull-Up @ V
DDEXT
= Max, V
IN
= 0 V 200 μA
I
OZH
5, 6
Three-State Leakage Current @ V
DDEXT
= Max, V
IN
= V
DDEXT
Max 10 μA
I
OZL
5
Three-State Leakage Current @ V
DDEXT
= Max, V
IN
= 0 V 10 μA
I
OZLPU
6
Three-State Leakage Current Pull-Up @ V
DDEXT
= Max, V
IN
= 0 V 200 μA
I
DD-INTYP
7, 8
Supply Current (Internal) t
CCLK
= Min, V
DDINT
= Nom 800 mA
I
AVDD
9
Supply Current (Analog) A
VDD
= Max 10 mA
C
IN
10,
11
Input Capacitance f
IN
= 1 MHz, T
CASE
= 25°C, V
IN
= 1.2 V 4.7 pF
1
Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, and XTAL.
2
See Output Drive Currents on Page 46 for typical drive current capabilities.
3
Applies to input pins: SPIDS, BOOT_CFGx, CLK_CFGx, TCK, RESET, and CLKIN.
4
Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.
5
Applies to three-stateable pins: FLAG3–0.
6
Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, and MOSI.
7
Typical internal current data reflects nominal operating conditions.
8
See the Engineer-to-Engineer Note “Estimating Power for the ADSP-21362 SHARC Processors” (EE-277) for further information.
9
Characterized, but not tested.
10
Applies to all signal pins.
11
Guaranteed, but not tested.