Datasheet

Rev. J | Page 16 of 60 | July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
PACKAGE INFORMATION
The information presented in Figure 4 provides details about
the package branding for the ADSP-2136x processor. For a
complete listing of product availability, see Ordering Guide on
Page 56.
ESD CAUTION
MAXIMUM POWER DISSIPATION
See the Engineer-to-Engineer Note “Estimating Power for the
ADSP-21362 SHARC Processors” (EE-277) for detailed thermal
and power information regarding maximum power dissipation.
For information on package thermal specifications, see Thermal
Characteristics on Page 47.
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 8 may cause perma-
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. For
voltage reference levels, see Figure 39 on Page 46 under Test
Conditions.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 5). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f
VCO
specified in Table 11.
Figure 4. Typical Package Brand
Table 7. Package Brand Information
Brand Key Field Description
t Temperature Range
pp Package Type
Z RoHS Compliant Designation
cc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
# RoHS Compliant Designation
yyww Date Code
tppZ-cc
S
ADSP-2136x
a
#yyww country_of_origin
vvvvvv.x n.n
ESD
(electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid
performance degradation or loss of functionality.
Table 8. Absolute Maximum Ratings
Parameter Rating
Internal (Core) Supply Voltage (V
DDINT
)–0.3 V to +1.5 V
Analog (PLL) Supply Voltage (A
VDD
)–0.3 V to +1.5 V
External (I/O) Supply Voltage (V
DDEXT
)–0.3 V to +4.6 V
Input Voltage –0.5 V to +3.8 V
Output Voltage Swing –0.5 V to V
DDEXT
+ 0.5 V
Load Capacitance 200 pF
Storage Temperature Range –65°C to +150°C
Junction Temperature While Biased 125°C