Datasheet

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 23 of 60 | July 2013
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01 through DAI_P20).
Table 18. Precision Clock Generator (Direct Pin Routing)
K and B Grade Y Grade
Parameter Min Max Max Unit
Timing Requirements
t
PCGIP
Input Clock Period t
PCLK
× 4 ns
t
STRIG
PCG Trigger Setup Before Falling
Edge of PCG Input Clock
4.5 ns
t
HTRIG
PCG Trigger Hold After Falling
Edge of PCG Input Clock
3 ns
Switching Characteristics
t
DPCGIO
PCG Output Clock and Frame Sync
Active Edge Delay After PCG Input
Clock
2.5 10 10 ns
t
DTRIGCLK
PCG Output Clock Delay After PCG
Trigger
2.5 + (2.5 × t
PCGIP
) 10 + (2.5 × t
PCGIP
) 12 + (2.5 × t
PCGIP
)ns
t
DTRIGFS
PCG Frame Sync Delay After PCG
Trigger
2.5 + ((2.5 + D – PH) × t
PCGIP
) 10 + ((2.5 + D – PH) × t
PCGIP
) 12 + ((2.5 + D – PH) × t
PCGIP
)ns
t
PCGOP
1
Output Clock Period 2 × t
PCGIP
– 1 ns
D = FSxDIV, PH = FSxPHASE. For more information, refer to the
ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Gener-
ators” chapter.
1
In normal mode, t
PCGOP
(min) = 2 × t
PCGIP
.
Figure 15. Precision Clock Generator (Direct Pin Routing)
DAI_Pn
PCG_TRIGx_I
DAI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
PCG_CLKx_O
DAI_Pz
PCG_FSx_O
t
DTRIGFS
t
DTRIGCLK
t
DPCGIO
t
STRIG
t
HTRIG
t
PCGOP
t
DPCGIO
t
PCGIP