Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 25 of 60 | July 2013
Memory Read—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the processor is
accessing external memory space.
Table 20. 8-Bit Memory Read Cycle
Parameter
K and B Grade Y Grade
Min Max Min Max Unit
Timing Requirements
t
DRS
AD7–0 Data Setup Before RD High 3.3 4.5 ns
t
DRH
AD7–0 Data Hold After RD High 0 0 ns
t
DAD
AD15–8 Address to AD7–0 Data Valid D + t
PCLK
– 5.0 D + t
PCLK
– 5.0 ns
Switching Characteristics
t
ALEW
ALE Pulse Width 2 × t
PCLK
– 2.0 2 × t
PCLK
– 2.0 ns
t
ADAS
1
AD15–0 Address Setup Before ALE Deasserted t
PCLK
– 2.5 t
PCLK
– 2.5 ns
t
RRH
Delay Between RD Rising Edge to Next
Falling Edge
H + t
PCLK
– 1.4 H + t
PCLK
– 1.4 ns
t
ALERW
ALE Deasserted to Read Asserted 2 × t
PCLK
– 3.8 2 × t
PCLK
– 3.8 ns
t
RWALE
Read Deasserted to ALE Asserted F + H + 0.5 F + H + 0.5 ns
t
ADAH
1
AD15–0 Address Hold After ALE Deasserted t
PCLK
– 2.3 t
PCLK
– 2.3 ns
t
ALEHZ
1
ALE Deasserted to AD7–0 Address in High-Z t
PCLK
t
PCLK
+ 3.0 t
PCLK
t
PCLK
+ 3.8 ns
t
RW
RD Pulse Width D – 2.0 D – 2.0 ns
t
RDDRV
AD7–0 ALE Address Drive After Read High F + H + t
PCLK
– 2.3 F + H + t
PCLK
– 2.3 ns
t
ADRH
AD15–8 Address Hold After RD High H H ns
t
DAWH
AD15–8 Address to RD High D + t
PCLK
– 4.0 D + t
PCLK
– 4.0 ns
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
PCLK
H = t
PCLK
(if a hold cycle is specified, else H = 0)
F = 7 × t
PCLK
(if FLASH_MODE is set, else F = 0)
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
Figure 17. Read Cycle for 8-Bit Memory Timing
ALE
RD
WR
AD15–8
AD7–0
t
ALEW
t
ALERW
t
RWALE
t
RW
t
RRH
t
RDDRV
t
DAWH
t
ADAS
t
ADAH
VALID ADDRESSVALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
DATA
t
ADRH
t
DAD
t
DRS
t
DRH
t
ALEHZ
NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE SHOWS ONLY
TWO MEMORY READS TO PROVIDE THE NECESSARY TIMING INFORMATION.