Datasheet

Rev. J | Page 26 of 60 | July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 21. 16-Bit Memory Read Cycle
Parameter
K and B Grade Y Grade
Min Max Min Max Unit
Timing Requirements
t
DRS
AD15–0 Data Setup Before RD High 3.3 4.5 ns
t
DRH
AD15–0 Data Hold After RD High 0 0 ns
Switching Characteristics
t
ALEW
ALE Pulse Width 2 × t
PCLK
– 2.0 2 × t
PCLK
– 2.0 ns
t
ADAS
1
AD15–0 Address Setup Before ALE Deasserted t
PCLK
– 2.5 t
PCLK
– 2.5 ns
t
ALERW
ALE Deasserted to Read Asserted 2 × t
PCLK
– 3.8 2 × t
PCLK
– 3.8 ns
t
RRH
2
Delay Between RD Rising Edge to Next Falling
Edge
H + t
PCLK
– 1.4 H + t
PCLK
– 1.4 ns
t
RWALE
Read Deasserted to ALE Asserted F + H + 0.5 F + H + 0.5 ns
t
RDDRV
ALE Address Drive After Read High F + H + t
PCLK
– 2.3 F + H + t
PCLK
– 2.3 ns
t
ADAH
1
AD15–0 Address Hold After ALE Deasserted t
PCLK
– 2.3 t
PCLK
– 2.3 ns
t
ALEHZ1
ALE Deasserted to Address/Data15–0 in High-Z t
PCLK
t
PCLK
+ 3.0 t
PCLK
t
PCLK
+ 3.8 ns
t
RW
RD Pulse Width D – 2.0 D – 2.0 ns
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
PCLK
H = t
PCLK
(if a hold cycle is specified, else H = 0)
F = 7 × t
PCLK
(if FLASH_MODE is set, else F = 0)
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
2
This parameter is only available when in EMPP = 0 mode.
Figure 18. Read Cycle for 16-Bit Memory Timing
t
RWALE
t
RDDRV
VALID
ADDRESS
VALID DATAVALID DATAVALID ADDRESS
ALE
RD
WR
AD15–0
t
ADAS
t
ADAH
t
ALEHZ
t
DRS
t
DRH
t
ALEW
t
ALERW
t
RW
t
RRH
NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP ⬆ 0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES.
WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE.