Datasheet

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 27 of 60 | July 2013
Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the processor is
accessing external memory space.
Table 22. 8-Bit Memory Write Cycle
Parameter
K and B Grade Y Grade
Min Min Unit
Switching Characteristics
t
ALEW
ALE Pulse Width 2 × t
PCLK
– 2.0 2 × t
PCLK
– 2.0 ns
t
ADAS
1
AD15–0 Address Setup Before ALE Deasserted t
PCLK
– 2.8 t
PCLK
– 2.8 ns
t
ALERW
ALE Deasserted to Write Asserted 2 × t
PCLK
– 3.8 2 × t
PCLK
– 3.8 ns
t
RWALE
Write Deasserted to ALE Asserted H + 0.5 H + 0.5 ns
t
WRH
Delay Between WR Rising Edge to Next WR Falling Edge F + H + t
PCLK
– 2.3 F + H + t
PCLK
– 2.3 ns
t
ADAH
1
AD15–0 Address Hold After ALE Deasserted t
PCLK
– 0.5 t
PCLK
– 0.5 ns
t
WW
WR Pulse Width D – F – 2.0 D – F – 2.0 ns
t
ADWL
AD15–8 Address to WR Low t
PCLK
– 2.8 t
PCLK
– 3.5 ns
t
ADWH
AD15–8 Address Hold After WR High H H ns
t
DWS
AD7–0 Data Setup Before WR High D – F + t
PCLK
– 4.0 D – F + t
PCLK
– 4.0 ns
t
DWH
AD7–0 Data Hold After WR High H H ns
t
DAWH
AD15–8 Address to WR High D – F + t
PCLK
– 4.0 D – F + t
PCLK
– 4.0 ns
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
PCLK
.
H = t
PCLK
(if a hold cycle is specified, else H = 0)
F = 7 × t
PCLK
(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be  9 × t
PCLK
.
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
Figure 19. Write Cycle for 8-Bit Memory Timing
AD15 - 8
VALID
ADDRESS
VALID ADDRESS
t
ADAS
AD7 - 0
ALE
RD
WR
t
ADAH
t
ADWH
t
ADWL
VALID DATA
t
DAWH
t
WRH
t
RWALE
VALID
ADDRESS
VALID DATA
t
ALEW
t
ALERW
t
WW
t
DWS
t
DWH
VALID ADDRESS
NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE
SHOWS ONLY TWO MEMORY WRITES TO PROVIDE THE NECESSARY TIMING INFORMATION.