Datasheet

Rev. J | Page 28 of 60 | July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 23. 16-Bit Memory Write Cycle
Parameter
K and B Grade Y Grade
Min Min Unit
Switching Characteristics
t
ALEW
ALE Pulse Width 2 × t
PCLK
– 2.0 2 × t
PCLK
– 2.0 ns
t
ADAS
1
AD15–0 Address Setup Before ALE Deasserted t
PCLK
– 2.5 t
PCLK
– 2.5 ns
t
ALERW
ALE Deasserted to Write Asserted 2 × t
PCLK
– 3.8 2 × t
PCLK
– 3.8 ns
t
RWALE
Write Deasserted to ALE Asserted H + 0.5 H + 0.5 ns
t
WRH
2
Delay Between WR Rising Edge to Next WR Falling Edge F + H + t
PCLK
– 2.3 F + H + t
PCLK
– 2.3 ns
t
ADAH
1
AD15–0 Address Hold After ALE Deasserted t
PCLK
– 2.3 t
PCLK
– 2.3 ns
t
WW
WR Pulse Width D – F – 2.0 D – F – 2.0 ns
t
DWS
AD15–0 Data Setup Before WR High D – F + t
PCLK
– 4.0 D – F + t
PCLK
– 4.0 ns
t
DWH
AD15–0 Data Hold After WR High H H ns
D = (the value set by the PPDUR Bits (5–1) in the PPCTL register) × t
PCLK
.
H = t
PCLK
(if a hold cycle is specified, else H = 0)
F = 7 × t
PCLK
(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be  9 × t
PCLK
.
t
PCLK
= (peripheral) clock period = 2 × t
CCLK
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
2
This parameter is only available when in EMPP = 0 mode.
Figure 20. Write Cycle for 16-Bit Memory Timing
AD15 - 0
VALID
ADDRESS
VALID DATA
t
ADAS
ALE
RD
WR
t
ADAH
t
WRH
t
RWALE
t
ALEW
t
ALERW
t
WW
t
DWS
t
DWH
VALID DATA
VALID
ADDRESS
NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP  0, ONLY ONE WR PULSE OCCURS BETWEEN ALE CYCLES.
WHEN EMPP = 0, MULTIPLE WR PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE.