Datasheet

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 35 of 60 | July 2013
Pulse-Width Modulation Generators
Sample Rate Converter—Serial Input Port
The SRC input signals are routed from the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided in
Table 31 are valid at the DAI_P20–1 pins. This feature is not
available on the ADSP-21363 models.
Table 30. PWM Timing
1
Parameter Min Max Unit
Switching Characteristics
t
PWMW
PWM Output Pulse Width t
PCLK
– 2 (2
16
– 2) × t
PCLK
ns
t
PWMP
PWM Output Period 2 × t
PCLK
– 1.5 (2
16
– 1) × t
PCLK
ns
1
Note that the PWM output signals are shared on the parallel port bus (AD15-0 pins).
Figure 26. PWM Timing
PWM
OUTPUTS
t
PWMW
t
PWMP
Table 31. SRC, Serial Input Port
Parameter Min Unit
Timing Requirements
t
SRCSFS
1
Frame Sync Setup Before Serial Clock Rising Edge 3 ns
t
SRCHFS
1
Frame Sync Hold After Serial Clock Rising Edge 3 ns
t
SRCSD
1
SDATA Setup Before Serial Clock Rising Edge 3 ns
t
SRCHD
1
SDATA Hold After Serial Clock Rising Edge 3 ns
t
SRCCLKW
Clock Width 36 ns
t
SRCCLK
Clock Period 80 ns
1
The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via the PCGs or SPORTs. The PCG’s
input can be either CLKIN or any of the DAI pins.