Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
Rev. J | Page 42 of 60 | July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPI Interface—Master
The processor contains two SPI ports. The primary has dedi-
cated pins and the secondary is available through the DAI. The
timing provided in Table 39 and Table 40 applies to both ports.
Table 39. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
K and B Grade Y Grade
Min Max Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time) 5.2 6.2 ns
t
SSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time) (SPI2) 8.2 9.5 ns
t
HSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid 2 2 ns
Switching Characteristics
t
SPICLKM
Serial Clock Cycle 8 × t
PCLK
– 2 8 × t
PCLK
– 2 ns
t
SPICHM
Serial Clock High Period 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
SPICLM
Serial Clock Low Period 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
DDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time) 3.0 3.0 ns
t
DDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time) (SPI2) 8.0 9.5 ns
t
HDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
SDSCIM
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge 4 × t
PCLK
– 2.5 4 × t
PCLK
– 3.0 ns
t
SDSCIM
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2) 4 × t
PCLK
– 2.5 4 × t
PCLK
– 3.0 ns
t
HDSM
Last SPICLK Edge to FLAG3–0IN High 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
SPITDM
Sequential Transfer Delay 4 × t
PCLK
– 1 4 × t
PCLK
– 1 ns
Figure 34. SPI Master Timing
t
SPICHM
t
SDSCIM
t
SPICLM
t
SPICLKM
t
HDSM
t
SPITDM
t
DDSPIDM
t
HSPIDM
t
SSPIDM
DPI
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
CPHASE = 1
CPHASE = 0
t
HDSPIDM
t
HSPIDM
t
HSPIDM
t
SSPIDM
t
SSPIDM
t
DDSPIDM
t
HDSPIDM
SPICLK
(CP = 0,
CP = 1)
(OUTPUT)