Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 43 of 60 | July 2013
SPI Interface—Slave
Table 40. SPI Interface Protocol—Slave Switching and Timing Specifications
K and B Grade Y Grade
Parameter Min Max Max Unit
Timing Requirements
t
SPICLKS
Serial Clock Cycle 4 × t
PCLK
– 2 ns
t
SPICHS
Serial Clock High Period 2 × t
PCLK
– 2 ns
t
SPICLS
Serial Clock Low Period 2 × t
PCLK
– 2 ns
t
SDSCO
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
2 × t
PCLK
2 × t
PCLK
ns
ns
t
HDS
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × t
PCLK
ns
t
SSPIDS
Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 ns
t
HSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid 2 ns
t
SDPPW
SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × t
PCLK
ns
Switching Characteristics
t
DSOE
SPIDS Assertion to Data Out Active 0 5 5 ns
t
DSOE
1
SPIDS Assertion to Data Out Active (SPI2) 0 8 9 ns
t
DSDHI
SPIDS Deassertion to Data High Impedance 0 5 5.5 ns
t
DSDHI
1
SPIDS Deassertion to Data High Impedance (SPI2) 0 8.6 10 ns
t
DDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 11.0 ns
t
HDSPIDS
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t
PCLK
ns
t
DSOV
SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t
PCLK
5 × t
PCLK
ns
1
The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, refer to the ADSP-2136x SHARC Processor Hardware
Reference, “Serial Peripheral Interface Port” chapter.