Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
Rev. J | Page 50 of 60 | July 2013
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
136-BALL BGA PIN CONFIGURATIONS
The following table shows the processor’s ball names and, when
applicable, their default function after reset in parentheses.
Table 46. BGA Pin Assignments
Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No.
CLK_CFG0 A01 CLK_CFG1 B01 BOOT_CFG1 C01 V
DDINT
D01
XTAL A02 GND B02 BOOT_CFG0 C02 GND D02
TMS A03 V
DDEXT
B03 GND C03 GND D04
TCK A04 CLKIN B04 GND C12 GND D05
TDI A05 TRST
B05 GND C13 GND D06
RESETOUT
A06 A
VSS
B06 V
DDINT
C14 GND D09
TDO A07 A
VDD
B07 GND D10
EMU
A08 V
DDEXT
B08 GND D11
MOSI A09 SPICLK B09 GND D13
MISO A10 RESET
B10 V
DDINT
D14
SPIDS
A11 V
DDINT
B11
V
DDINT
A12 GND B12
GND A13 GND B13
GND A14 GND B14
V
DDINT
E01 FLAG1 F01 AD7 G01 AD6 H01
GND E02 FLAG0 F02 V
DDINT
G02 V
DDEXT
H02
GND E04 GND F04 V
DDEXT
G13 DAI_P18 (SD5B) H13
GND E05 GND F05 DAI_P19 (SCLK5) G14 DAI_P17 (SD5A) H14
GND E06 GND F06
GND E09 GND F09
GND E10 GND F10
GND E11 GND F11
GND E13 FLAG2 F13
FLAG3 E14 DAI_P20 (SFS5) F14