Datasheet
Table Of Contents
- Summary
- Dedicated Audio Components
- Table of Contents
- Revision History
- General Description
- SHARC Family Core Architecture
- SIMD Computational Engine
- Independent, Parallel Computation Units
- Data Register File
- Context Switch
- Universal Registers
- Timer
- Single-Cycle Fetch of Instruction and Four Operands
- Instruction Cache
- Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
- Flexible Instruction Set
- On-Chip Memory
- On-Chip Memory Bandwidth
- ROM-Based Security
- Family Peripheral Architecture
- I/O Processor Features
- System Design
- Development Tools
- Additional Information
- Related Signal Chains
- SHARC Family Core Architecture
- Pin Function Descriptions
- Specifications
- Operating Conditions
- Electrical Characteristics
- Package Information
- ESD Caution
- Maximum Power Dissipation
- Absolute Maximum Ratings
- Timing Specifications
- Core Clock Requirements
- Power-Up Sequencing
- Clock Input
- Clock Signals
- Reset
- Interrupts
- Core Timer
- Timer PWM_OUT Cycle Timing
- Timer WDTH_CAP Timing
- DAI Pin to Pin Direct Routing
- Precision Clock Generator (Direct Pin Routing)
- Flags
- Memory Read—Parallel Port
- Memory Write—Parallel Port
- Serial Ports
- Input Data Port (IDP)
- Parallel Data Acquisition Port (PDAP)
- Pulse-Width Modulation Generators
- Sample Rate Converter—Serial Input Port
- Sample Rate Converter—Serial Output Port
- S/PDIF Transmitter
- S/PDIF Receiver
- SPI Interface—Master
- SPI Interface—Slave
- JTAG Test Access Port and Emulation
- Output Drive Currents
- Test Conditions
- Capacitive Loading
- Thermal Characteristics
- 144-Lead LQFP_EP Pin Configurations
- 136-Ball BGA Pin Configurations
- Package Dimensions
- Automotive Products
- Ordering Guide
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. J | Page 51 of 60 | July 2013
Figure 45 and Figure 46 show BGA pin assignments from the
bottom and top, respectively.
Note: Use the center block of ground pins to provide thermal
pathways to your printed circuit board’s ground plane.
AD5 J01 AD3 K01 AD2 L01 AD0 M01
AD4 J02 V
DDINT
K02 AD1 L02 WR M02
GND J04 GND K04 GND L04 GND M03
GND J05 GND K05 GND L05 GND M12
GND J06 GND K06 GND L06 DAI_P12 (SD3B) M13
GND J09 GND K09 GND L09 DAI_P13 (SCLK3) M14
GND J10 GND K10 GND L10
GND J11 GND K11 GND L11
V
DDINT
J13 GND K13 GND L13
DAI_P16 (SD4B) J14 DAI_P15 (SD4A) K14 DAI_P14 (SFS3) L14
AD15 N01 AD14 P01
ALE N02 AD13 P02
RD
N03 AD12 P03
V
DDINT
N04 AD11 P04
V
DDEXT
N05 AD10 P05
AD8 N06 AD9 P06
V
DDINT
N07 DAI_P1 (SD0A) P07
DAI_P2 (SD0B) N08 DAI_P3 (SCLK0) P08
V
DDEXT
N09 DAI_P5 (SD1A) P09
DAI_P4 (SFS0) N10 DAI_P6 (SD1B) P10
V
DDINT
N11 DAI_P7 (SCLK1) P11
V
DDINT
N12 DAI_P8 (SFS1) P12
GND N13 DAI_P9 (SD2A) P13
DAI_P10 (SD2B) N14 DAI_P11 (SD3A) P14
Table 46. BGA Pin Assignments (Continued)
Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No.