Datasheet

ADSP-21371
DATA MODES
The upper 32 data pins of the external memory interface are
muxed (using bits in the SYSCTL register) to support the exter-
nal memory interface data (input/output), the PDAP (input
only), and the FLAGS (input/output). Table 6 provides the pin
settings.
Table 6. Function of Data Pins
DATA PIN MODE DATA31–16 DATA15–8 DATA7–0
000 EPDATA32–0
001 FLAGS/PWM15–0
1
EPDATA15–0
010 FLAGS/PWM15–0
1
FLAGS15–8 EPDATA7–0
011 FLAGS/PWM15–0
1
FLAGS15–0
100 PDAP (DATA + CTRL) EPDATA7–0
101 PDAP (DATA + CTRL) FLAGS7–0
110 Reserved
111 Three-state all pins
1
These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals
FLAGS/PWM_SEL. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors.
BOOT MODES
Table 7. Boot Mode Selection
BOOTCFG1–0 Booting Mode
00 SPI Slave Boot
01 SPI Master Boot
10 EPROM/FLASH Boot
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see Timing Specifications and
Figure 3 on Page 17.
Table 8. Core Instruction Rate/ CLKIN Ratio Selection
CLKCFG1–0 Core to CLKIN Ratio
00 6:1
01 32:1
10 16:1
Rev. 0 | Page 14 of 48 | June 2007