Datasheet
ADSP-21371
Figure 3 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
TIMING SPECIFICATIONS
The ADSP-21371’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, and serial ports. During reset, program the ratio between
the processor’s internal clock frequency and external (CLKIN)
clock frequency with the CLKCFG1–0 pins (see Table 8 on
Page 14). To determine switching frequencies for the serial
ports, divide down the internal clock, using the programmable
divider control of each port (DIVx for the serial ports).
The ADSP-21371’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor’s internal clock.
Core clock frequency can be calculated as:
CCLK = 1 t
CCLK
= f
INPUT
(PLLM/PLLD)
÷2
+
–
0
1
INDIV[8]
LOOP
FILTER
VCO
÷1, 2,4,8
N
PLLD[7..6]
DIVEN[9]
01
1
PLLBP[15]
AMP
÷1
-
64
M
PLLM[ 5..0]
C
L
K
_
C
F
G
[
1
.
.
0
]
00 = 6
01 = 32
10 = 16
11 = 6
DE LAY
4096 CLKIN
CLKOUTEN[12 ]
BUFF
÷2
0
1
CCLK
100M Hz
266M Hz
PCLK
(IOP )
CLKOUT
or
CO R ERS T
RS TOUT
CLKIN
3.125M Hz
66 . 7M H z
RES ET
XTAL
@BOOT, C LKCFG[]->PLLM[]
160 M Hz < VCO_OUT < 800M Hz
÷2, 2.5,
3, 3.5, 4
SDRATIO[20..18]
PL L BYP AS S; Reserv ed
MULTIPLIE R
BLOCK
control register (PMCTL). For more information, see the ADSP-
2136x SHARC Processor Programming Reference.
to
to
SDCLK
Figure 3. Core Clock and System Clock Relationship to CLKIN
Note that in the user application, the PLL multiplier value
should be selected in such a way that the VCO frequency falls in
between 160 MHz and 800 MHz. The VCO frequency is calcu-
lated as follows:
where:
f
VCO
= VCO frequency.
PLLM = multiplier value programmed.
PLLD = divider value programmed.
f
INPUT
= input frequency to the PLL.
f
INPUT
= CLKIN when the input divider is disabled.
f
INPUT
= CLKIN/2 when the input divider is enabled.
C
C
L
K
F
G
[
1
.
.
0
]
Rev. 0 | Page 17 of 48 | June 2007