Datasheet

ADSP-21371
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 13.
Table 13. Power Up Sequencing Timing Requirements (Processor Startup)
Parameter Min Max Unit
Timing Requirements
t
RSTVDD
RESET Low Before V
DDINT
/V
DDEXT
On
t
IVDDEVDD
V
DDINT
on Before V
DDEXT
t
CLKVDD
1
CLKIN Valid After V
DDINT
/V
DDEXT
Valid
t
CLKRST
CLKIN Valid Before RESET Deasserted
t
PLLRST
PLL Control Setup Before RESET Deasserted
Switching Characteristic
t
CORERST
Core Reset Deasserted After RESET Deasserted
0
–50
0
10
2
20
3
4096  t
CK
+ 2  t
CCLK
4, 5
200
200
ns
ms
ms
µs
µs
1
Valid V
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on t
SRST
specification in Table 15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in
4097 cycles maximum.
CLKIN
RESET
t
RSTVDD
RSTOUT
V
DDEXT
V
DDINT
t
PLLRST
t
CLKRST
t
CLKVDD
t
IVDDEVDD
CLK_CFG1-0
t
CORERST
Figure 4. Power-Up Sequencing
Rev. 0 | Page 19 of 48 | June 2007