Datasheet

ADSP-21371
Clock Input
Table 14. Clock Input
266 MHz
Unit
Parameter
Min Max
Timing Requirements
t
CK
CLKIN Period 22.5
1
320
2
ns
t
CKL
CLKIN Width Low 10
1
180
2
ns
t
CKH
CLKIN Width High 10
1
180
2
ns
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V) 6 ns
t
CCLK
3
CCLK Period 3.75
1
10 ns
1
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
2
Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
3
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
CLKIN
t
CK
t
CKH
t
CKL
Figure 5. Clock Input
Clock Signals
The ADSP-21371 can use an external clock or a crystal. See the
CLKIN pin description in Table 5. The programmer can config-
ure the ADSP-21371 to use its internal clock generator by
connecting the necessary components to CLKIN and XTAL.
Figure 6 shows the component connections used for a crystal
operating in fundamental mode. Note that the clock rate is
achieved using a 16.67 MHz crystal and a PLL multiplier ratio
16:1 (CCLK:CLKIN achieves a clock speed of 266 MHz). To
achieve the full core clock rate, programs need to configure the
multiplier bits in the PMCTL register.
C1
22pF
Y1
R1
1M�*
XTAL
CLKIN
C2
22pF
16.67 MHz
R2
47�*
ADSP-2137X
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICA TIONS
*TYPICAL VALUES
Figure 6. 266 MHz Operation (Fundamental Mode Crystal)
Rev. 0 | Page 20 of 48 | June 2007