Datasheet

ADSP-21371
Reset
Table 15. Reset
Parameter
Timing Requirements
t
WRST
1
RESET Pulse Width Low
t
SRST
RESET Setup Before CLKIN Low
Min
4  t
CK
8
Max Unit
ns
ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 ms while RESET is low, assuming
stable V
DD
and CLKIN (not including start-up time of external clock oscillator).
CLKIN
RESET
t
RUNWRST
t
RUNSRST
Figure 7. Reset
Running Reset
The following timing specification applies to CLKOUT/
RESETOUT/RUNRSTIN pin when it is configured as
RUNRSTIN
.
Table 16. Running Reset
Parameter
Timing Requirements
t
WRUNRST
Running RESET Pulse Width Low
t
SRUNRST
Running RESET Setup Before CLKIN High
Min
4  t
CK
8
Max Unit
ns
ns
CLKIN
RUNRSTIN
t
WRUNRST
t
SRUNRST
Figure 8. Running Reset
Rev. 0 | Page 21 of 48 | June 2007