Datasheet

ADSP-21371
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
Table 22. Precision Clock Generator (Direct Pin Routing)
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01 – DAI_P20).
Parameter Min Max Unit
Timing Requirements
t
PCGIW
Input Clock Period
t
STRIG
PCG Trigger Setup Before Falling Edge of PCG Input
Clock
t
HTRIG
PCG Trigger Hold After Falling Edge of PCG Input
Clock
Switching Characteristics
t
DPCGIO
PCG Output Clock and Frame Sync Active Edge Delay
After PCG Input Clock
t
DTRIGCLK
PCG Output Clock Delay After PCG Trigger
t
DTRIGFS
PCG Frame Sync Delay After PCG Trigger
t
PCGOW
1
Output Clock Period
24
4.5
3
2.5
2.5 + ((2.5) × t
PCGIW
)
2.5 + ((2.5 + D – PH) × t
PCGIW
)
2 × t
PCGIW
– 1
10
10 + ((2.5) × t
PCGIW
)
10 + ((2.5 + D – PH) × t
PCGIW
)
ns
ns
ns
ns
ns
ns
ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21368 Processor,
“Precision Clock Generators” chapter.
1
Normal mode of operation.
DAI_Pn
DPI_Pn
PCG_TRIGx_I
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
DPI_Py
PCG_CLKx_O
DAI_Pz
DPI_Pz
PCG_FSx_O
t
STRIG
t
HTRIG
t
DPCGIO
t
DTRIGFS
t
PCGIW
t
PCGOW
t
DTRIGCLK
t
DPCGIO
Figure 14. Precision Clock Generator (Direct Pin Routing)
Rev. 0 | Page 24 of 48 | June 2007