Datasheet

ADSP-21371
SDRAM Interface Timing (133 MHz SDCLK)
Table 24. SDRAM Interface Timing
1
Parameter Min Max Unit
Timing Requirements
t
SSDAT
DATA Setup Before SDCLK
t
HSDAT
DATA Hold After SDCLK
Switching Characteristics
t
SDCLK
SDCLK Period
t
SDCLKH
SDCLK Width High
t
SCCLKL
SDCLK Width Low
t
DCAD
Command, ADDR, Data Delay After SDCLK
2
t
HCAD
Command, ADDR, Data Hold After SDCLK
2
t
DSDAT
Data Disable After SDCLK
t
ENSDAT
Data Enable After SDCLK
0.58
2.2
7.5
3
3
1.3
1.6
5.3
5.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
For F
CCLK
= 133 MHz (SDCLK ratio = 1:2).
2
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, and SDCKE.
t
HCAD
t
HCAD
t
DSDAT
t
DCAD
t
SSDAT
t
DCAD
t
ENSDAT
t
HSDAT
t
SD CLKL
t
SDCLKH
t
SDCLK
SDC LK
DATA (IN)
DA TA(OUT)
CM ND ADDR
(OUT )
Figure 16. SDRAM Interface Timing for 133 MHz SDCLK
Rev. 0 | Page 26 of 48 | June 2007