Datasheet

ADSP-21371
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD
, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 25. Memory Read
—Bus Master
Parameter Min Max Unit
Timing Requirements
t
DAD
Address, Selects Delay to Data Valid
1, 2
t
DRLD
RD Low to Data Valid
1
t
SDS
Data Setup to RD High
t
HDRH
Data Hold from RD High
3, 4
t
DAAK
ACK Delay from Address, Selects
2, 5
t
DSAK
ACK Delay from RD Low
4
Switching Characteristics
t
DRHA
Address Selects Hold After RD High
t
DARL
Address Selects to RD Low
2
t
RW
RD Pulse Width
t
RWR
RD High to WR, RD, Low
2.2
0
RHC + 0.38
t
SDCLK
–3.3
W – 1.4
HI + t
SDCLK
–0.8
W+t
SDCLK
–5.12
W – 3
t
SDCLK
–10.1+ W
W – 7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W = (number of wait states specified in AMICTLx register) × t
SDCLK
.
HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) x t
SDCLK
IC = (number of idle cycles specified in AMICTLx register) x t
SDCLK
).
H = (number of hold cycles specified in AMICTLx register) x t
SDCLK
.
1
Data delay/setup: System must meet t
DAD
, t
DRLD
, or t
SDS.
2
The falling edge of MSx, is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
4
Data hold: User must meet t
HDRH
in asynchronous access mode. See Test Conditions on Page 44 for the calculation of hold times given capacitive and dc loads.
5
ACK delay/setup: User must meet t
DAAK
, or t
DSAK
, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t
DAAK
or t
DSAK
.
ADDRESS
MSx
RD
DATA
ACK
WR
t
DARL
t
RW
t
DAD
t
DAAK
t
HDRH
t
RWR
t
DRLD
t
DRHA
t
DSAK
t
SDS
Figure 17. Memory Read—Bus Master
Rev. 0 | Page 27 of 48 | June 2007