Datasheet

ADSP-21371
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD
, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 26. Memory Write
—Bus Master
Parameter Min Max Unit
Timing Requirements
t
DAAK
ACK Delay from Address, Selects
1, 2
t
DSAK
ACK Delay from WR Low
1, 3
Switching Characteristics
t
DAWH
Address, Selects to WR Deasserted
2
t
DAWL
Address, Selects to WR Low
2
t
WW
WR Pulse Width
t
DDWH
Data Setup Before WR High
t
DWHA
Address Hold After WR Deasserted
t
DWHD
Data Hold After WR Deasserted
t
DATRWH
Data Disable After WR Deasserted
4
t
WWR
WR High to WR, RD Low
t
DDWR
Data Disable Before RD Low
t
WDE
WR Low to Data Enabled
t
SDCLK
–3.6+ W
t
SDCLK
–2.7
W – 1.3
t
SDCLK
–3.0+ W
H + 0.15
H + 0.02
t
SDCLK
–1.37+ H
t
SDCLK
–1.5+ H
2t
SDCLK
– 5.1
t
SDCLK
– 4.1
t
SDCLK
– 10.1 + W
W – 7.1
t
SDCLK
+4.9+ H
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W = (number of wait states specified in AMICTLx register) × t
S SDCLK
H = (number of hold cycles specified in AMICTLx register) x t
SDCLK
1
ACK delay/setup: System must meet t
DAAK
, or t
DSAK
, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t
DAAK
or t
DSAK
.
2
The falling edge of MSx is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
4
See Test Conditions on Page 44 for calculation of hold times given capacitive and dc loads.
ADDRESS
MSx
WR
DATA
ACK
RD
t
DAWL
t
WW
t
DAAK
t
WWR
t
WDE
t
DDWR
t
DWHA
t
DAWH
t
DSAK
t
DDWH
t
DWHD
t
DATRWH
Figure 18. Memory Write—Bus Master
Rev. 0 | Page 28 of 48 | June 2007