Datasheet

ADSP-21371
Serial Ports
To determine whether communication is possible between two Serial port signals (SCLK, FS, Data Channel A, Data Channel B)
devices at clock speed n, the following specifications must be are routed to the DAI_P20–1 pins using the SRU. Therefore, the
confirmed: 1) frame sync delay and frame sync setup and hold, timing specifications provided below are valid at the
2) data delay and data setup and hold, and 3) SCLK width. DAI_P20–1 pins.
Table 27. Serial Ports—External Clock
Parameter Min Max Unit
Timing Requirements
t
SFSE
1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode) 2.5 ns
t
HFSE
1
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode) 2.5 ns
t
SDRE
1
Receive Data Setup Before Receive SCLK 2.5 ns
t
HDRE
1
Receive Data Hold After SCLK 2.5 ns
t
SCLKW
SCLK Width 10 ns
t
SCLK
SCLK Period 20 ns
Switching Characteristics
t
DFSE
2
FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode) 10.5 ns
t
HOFSE
2
FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode) 2 ns
t
DDTE
2
Transmit Data Delay After Transmit SCLK 11 ns
t
HDTE
2
Transmit Data Hold After Transmit SCLK 2 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 28. Serial Ports—Internal Clock
Parameter Min Max Unit
Timing Requirements
t
SFSI
1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
t
HFSI
1
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
t
SDRI
1
Receive Data Setup Before SCLK
t
HDRI
1
Receive Data Hold After SCLK
Switching Characteristics
t
DFSI
2
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
t
HOFSI
2
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
t
DFSIR
2
FS Delay After SCLK (Internally Generated FS in Receive Mode)
t
HOFSIR
2
FS Hold After SCLK (Internally Generated FS in Receive Mode)
t
DDTI
2
Transmit Data Delay After SCLK
t
HDTI
2
Transmit Data Hold After SCLK
t
SCKLIW
Transmit or Receive SCLK Width
7
2.5
7
2.5
–1.0
–1.0
–1.0
0.5t
SCLK
– 2
4
10.7
3.6
0.5t
SCLK
+ 2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Referenced to the sample edge.
2
Referenced to drive edge.
Rev. 0 | Page 29 of 48 | June 2007