Datasheet

ADSP-21371
DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE
DAI_P20 - 1
(SCLK)
DAI_P20
- 1
(FS)
DAI_P20 - 1
(DATA CHANNEL A/B)
DAI_P20
- 1
(SCLK)
DAI_P20
- 1
(FS)
DAI_P20
- 1
DAI_P20
- 1
(DATA CHANNEL A/B) (DATA CHANNEL A/B)
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
SDRI
t
HDRI
t
SFSI
t
HFSI
t
DFSIR
t
HOFSIR
t
SCLKIW
t
SDRE
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
t
DDTI
DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT—INTERNAL CLOCK
t
SFSI
t
HFSI
DATA TRANSMIT—EXTERNAL CLOCK
t
DFSI
t
HOFSI
t
SCLKIW
t
HDTI
t
DDTE
t
SFSE
t
HFSE
t
DFSE
t
HOFSE
t
SCLKW
t
HDTE
DAI_P20 - 1
(SCLK)
DAI_P20
- 1
(FS)
DAI_P20
- 1
(DATA CHANNEL A/B)
DAI_P20
- 1
(SCLK)
DAI_P20
- 1
(FS)
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE DRIVE EDGE
SCLK
DAI_P20
- 1
SCLK (EXT)
t
DDTTE
t
DDTEN
DAI_P20 - 1
(DATA CHANNEL A/B)
DRIVE EDGE
DAI_P20
- 1
SCLK (INT)
t
DDTIN
DAI_P20
- 1
(DATA CHANNEL A/B)
Figure 19. Serial Ports
Rev. 0 | Page 31 of 48 | June 2007