Datasheet
ADSP-21371
DAI_P20
-
1
(SCLK)
DAI_P20
-
1
(FS)
DAI_P20
-
1
(DATA CHANNEL A/B)
DAI_P20
-
1
(SCLK)
DAI_P20
-
1
(FS)
DA I_P20
-
1
(DATA CHANNEL A/B)
EXTERNAL RECEIV E FS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE DRIVE
DRIVE
SAMPLE DRIVE
LATE EXTERNAL TRANSMIT FS
1ST B IT
2ND BIT
1ST
BIT 2ND BIT
t
HFSE/I
t
SFSE/I
t
DDTE/I
t
DDTEN FS
t
DDTLFSE
t
HDTE/I
t
SFSE/I
t
DDTE/I
t
DDTENFS
t
DDTLFSE
t
HDTE/I
t
HFSE/I
NOTE: S ERIAL PORT SIGN ALS (S CLK , FS, DAT A CHANNEL A/B) ARE ROUTED TO THE DAI_P20
-
1PINS
USING THE SRU. THE TIMING SP ECIF ICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20
-
1PINS.
THE CHARACTERIZED AC SPORT TIMIN GS ARE APPLICABLE WHEN INTERNAL CLOCKS AND F RAMES
ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH SAU.
Figure 20. External Late Frame Sync
1
1
This figure reflects changes made to support left-justified sample pair mode.
Rev. 0 | Page 32 of 48 | June 2007